1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to an element isolation structure of a semiconductor device and a method of manufacturing the same.
2. Description of the Background Art
Conventionally, LOCOS (Local Oxidation of Silicon) is widely known as a method for providing isolation between elements. FIGS. 47 and 48 are cross sectional views showing the process flow in the case in which this LOCOS method is employed in a semiconductor device having an SOI (Semiconductor On Insulator) structure.
Referring first to FIG. 47, a semiconductor layer (hereinafter simply referred to as "SOI layer") 3 is formed on a main surface of a silicon substrate 1 with a buried oxide layer 2 therebetween, using SIMOX (Separation by Implanted Oxygen) method or the like. On this SOI layer 3, a nitride layer 11 patterned to obtain a prescribed shape is formed. Using this nitride layer 11 as a mask, ions of boron (B) are implanted to SOI layer 3. As a result, an impurity implantation region 4a which is to be a channel stopper region is formed.
Thereafter, LOCOS processing is performed on SOI layer 3 in a state as shown in FIG. 47. This forms an isolation oxide layer 20 selectively at SOI layer 3 as shown in FIG. 48. At this time, owing to the formation of isolation oxide layer 20, most of the impurity (boron) for forming the channel stopper region mentioned above is absorbed. Accordingly, ion implantation of boron (B) has to take place again in the vicinity of the edge portion of SOI layer 3 after isolating oxide film 20 is formed, thereby forming a channel stopper region 4 including an impurity (boron) of high concentration in the vicinity of the edge portion of SOI layer 3. As a result, it is made possible to effectively suppress the decrease of threshold voltage Vth of a parasitic MOS transistor in the vicinity of the edge portion of SOI layer 3.
However, when ion implantation of boron for forming channel stopper region 4 is performed after isolation oxide layer 20 is formed, there has been a problem as described in the following.
As shown in FIG. 48, one way to form channel stopper region 4 after the formation of isolation oxide layer 20 is to implant ions of boron selectively into the vicinity of the edge portion of SOI layer 3 only, with nitride layer 11 still remaining. Since this method enables channel stopper region 4 to be formed in a self-aligned manner, there is no need to form a new mask layer for ion implantation of boron described above. However, as shown in FIG. 48, implantation of boron ions by oblique ion implantation method is required in the vicinity of edge portion of SOI layer 3. Therefore, the above-described boron would be implanted to the region where the channel of MOS transistor is formed. As a result, there has been a problem that the effective channel width W would be small.
One method by which the problem as described above can be solved is a mesa isolation method shown in FIGS. 49 to 51. FIG. 49 is a cross-sectional view showing a semiconductor device in which a conventional mesa isolation method is adopted. FIGS. 50 and 51 are cross-sectional views showing the manufacturing process which is characteristic in the semiconductor device of FIG. 49.
Referring first to FIG. 49, a channel stopper region 4 is formed in the vicinity of the edge portion of an SOI layer 3. A recess portion 24 is formed directly under the edge portion of SOI layer 3. A gate insulation layer 7 is formed to cover SOI layer 3, and a gate electrode 8 is formed to cover this gate insulation layer 7.
Referring next to FIGS. 50 and 51, a method of manufacturing the semiconductor device shown in FIG. 49 will now be described. Referring first to FIG. 50, ion implantation of boron (B) for forming channel stopper region 4 is performed to SOI layer 3 by a method similar to the example of the above-described LOCOS. Thereafter, a nitride layer (not shown) is additionally formed to cover nitride layer 11, using CVD (Chemical Vapor Deposition). Then, by performing an anisotropical etching to the nitride layer, a nitride spacer 12 is formed as shown in FIG. 51. Thereafter, using nitride layer 11 and nitride spacer 12 as a mask, SOI layer 3 is patterned, followed by thermal oxidation for eliminating etching damages. Thus, a sidewall oxide layer 5 is formed at the sidewall of SOI layer 3, as shown in FIG. 51.
Thereafter, nitride layer 11, nitride spacer 12 and oxide layer 9 are removed by etching. As a result, recess portion 24 is formed directly beneath the edge portion of SOI layer 3.
Thereafter, gate insulation layer 7 is formed on the surface of SOI layer 3, and a gate electrode 8 is formed so as to cover this gate insulation layer 7. Then, in this case, source/drain regions are formed so as to sandwich the gate electrode 8 in SOI layer 3.
By the process as described above, a semiconductor device shown in FIG. 49 is formed. In this semiconductor device shown in FIG. 49, boron (B) for forming channel stopper region 4 is not implanted for the second time as in the case where the LOCOS method is adopted. Accordingly, the problem of small effective channel width W in the case where LOCOS is adopted can be solved.
However, even in the semiconductor device shown in FIG. 49, there has been a problem as described in the following. As shown in FIG. 51, sidewall oxide layer 5 is formed after the formation of channel stopper region 4. At this time, the impurity (boron) could be drawn out from channel stopper region 4 due to the formation of this sidewall oxide layer 5, although not as much as in the case of the above-described LOCOS method. Accordingly, concentration of the impurity (boron) within channel stopper region 4 is reduced, thus leading to a problem that threshold voltage Vth of the parasitic MOS transistor at the edge portion of SOI layer 3 is lowered. In addition, as shown in FIG. 49, recess portion 24 is formed directly beneath the edge portion of SOI layer 3. With such recess portion 24 formed, concentration of electric field is likely at the sidewall bottom portion 26 of SOI layer 3. This also leads to increase in the possibility of insulation breakdown, thus lowering the yield of the transistor.